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rubygems

rggen

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

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Activity

Latest release
4mo ago
Total releases
72
Cadence
~35 days
Last 12 months
2

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Details

License
MIT
First release
Apr 13, 2016
Releases
Version Released
0.36.1 patch
0.36.0 minor
0.35.2 patch
0.35.1 patch
0.35.0 minor
0.34.0 minor
0.33.4 patch
0.33.3 patch
0.33.2 patch
0.33.1 patch
0.33.0 minor
0.32.2 patch
0.32.0 minor
0.31.3 patch
0.25.4 patch
0.31.0 minor
0.30.2 patch
0.30.1 patch
0.30.0 minor
0.29.0 minor
0.28.0 minor
0.27.2 patch
0.27.1 patch
0.27.0 minor
0.26.2 patch
0.26.1 patch
0.26.0 minor
0.25.3 patch
0.25.2 patch
0.25.1 patch
0.25.0 minor
0.24.0 minor
0.23.2 patch
0.23.1 patch
0.23.0 minor
0.22.0 minor
0.21.1 patch
0.21.0 minor
0.20.0 minor
0.19.1 patch
0.19.0 minor
0.18.0 minor
0.17.0 minor
0.16.0 minor
0.15.0 minor
0.14.0 minor
0.13.0 minor
0.12.0 minor
0.11.0 minor
0.10.0 minor
1–50 of 72