pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator
Activity
- Latest release
- 5y ago
- Total releases
- 23
- Cadence
- ~2 months
- Last 12 months
- 0
Details
- License
- Apache-2.0
- First release
- Nov 10, 2014
Releases
| Version | Released | |
|---|---|---|
1.3.0
minor
| ||
1.2.1
patch
| ||
1.2.0
minor
| ||
1.1.4
patch
| ||
1.1.3
patch
| ||
1.1.2
patch
| ||
1.1.1
patch
| ||
1.1.0
minor
| ||
1.0.9
patch
| ||
1.0.8
patch
| ||
1.0.7
patch
| ||
1.0.6
patch
| ||
1.0.5
patch
| ||
1.0.4
patch
| ||
1.0.3
patch
| ||
1.0.2
patch
| ||
1.0.1
patch
| ||
1.0.0
major
| ||
0.9.6
patch
| ||
0.9.5
patch
| ||
0.9.3
patch
| ||
0.9.2
patch
| ||
0.9.1
initial
|