peakrdl-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
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Activity
- Latest release
- 5mo ago
- Total releases
- 29
- Cadence
- ~43 days
- Last 12 months
- 3
Reach
- Stars
- —
Details
- License
- LGPL-3.0
- First release
- Dec 05, 2021
Releases
| Version | Released | |
|---|---|---|
1.3.1
patch
| ||
1.3.0
minor
| ||
1.2.0
minor
| ||
1.1.1
patch
| ||
1.1.0
minor
| ||
1.0.0
major
| ||
0.23.0
minor
| ||
0.22.0
minor
| ||
0.21.0
minor
| ||
0.20.0
minor
| ||
0.19.0
minor
| ||
0.18.0
minor
| ||
0.17.0
minor
| ||
0.16.0
minor
| ||
0.15.0
minor
| ||
0.14.0
minor
| ||
0.13.0
minor
| ||
0.12.0
minor
| ||
0.11.0
minor
| ||
0.10.0
minor
| ||
0.9.0
minor
| ||
0.8.0
minor
| ||
0.7.0
minor
| ||
0.6.0
minor
| ||
0.5.0
minor
| ||
0.4.0
minor
| ||
0.3.0
minor
| ||
0.2.0
initial
| ||
0.1.0a1
pre
|