peakrdl-etana
Compile SystemRDL into a Verilog control/status register (CSR) block
- Latest release
- Jun 01, 2026
- Releases
- 9
- Known CVEs
- 0
- First release
- Oct 27, 2025
- License
- LGPL-3.0
Repository
Source
- Stars
- —
- Forks
- —
- Open issues
- —
Security score
No OpenSSF Scorecard available for this repository.
Packages from this repo
No other tracked packages from this repository.
Insights
Activity
- Total releases
- 9
- Last 12 months
- 9
- Cadence
- ~7 days
- Dependencies
- 4
Releases per month
last 12 monthsRelease mix
- minor 8
9
releases
Dependencies
Depends on
0.8.0-
jinja2
>=2.11
-
peakrdl
-
peakrdl-cli
>=1.2.3
-
systemrdl-compiler
~=1.31
Used by
Nothing tracked depends on this yet.
Releases
| Version | Released | |
|---|---|---|
0.8.0
minor
| ||
0.7.0
minor
| ||
0.6.0
minor
| ||
0.5.0
minor
| ||
0.4.0
minor
| ||
0.3.0
minor
| ||
0.2.0
minor
| ||
0.1.0
minor
| ||
0.0.8
initial
|