sv_port_sim
SvPortSim: Elixir interface for driving Verilated SystemVerilog modules through Ports, with each simulation instance managed as a GenServer.
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Activity
- Latest release
- 3mo ago
- Total releases
- 2
- Cadence
- ~daily
- Last 12 months
- 2
Reach
- Stars
- —
Details
- License
- Apache-2.0
- First release
- Jun 07, 2026
Releases
| Version | Released | |
|---|---|---|
0.2.0
minor
| ||
0.1.0
initial
|